Static random access memory (SRAM) is a type of semiconductor memory device that uses bi-stable latching circuitry to store each bit. An SRAM cell includes storage nodes formed by cross-coupled inverters which are accessed through pass gates coupled to a bit line and a complementary bit line, respectively. An SRAM cell operating at a relatively low voltage may suffer disturbance during an access operation. Specifically, during a read cycle, the storage node storing a logical low value is charged by one of the bit line and the complementary bit line, and if a voltage of the storage node rises above a switching threshold of the inverter driven by the storage node, stored data is destroyed, an issue referred to as read disturbance. Further, during a write cycle, other cells in the same row as the SRAM cell experience read disturbance, and data in the other cells is potentially destroyed, an issue referred to as dummy read disturbance.
Like reference symbols in the various drawings indicate like elements.